1. Field of the Invention:
The present invention relates to a nonvolatile semiconductor memory using a Fowler-Nordheim (FN) tunnel current for writing and erasing, and a driving method and fabrication method for such a nonvolatile semiconductor memory. More specifically, the present invention relates to a flash memory, and a driving method and fabrication method for the flash memory.
2. Description of the Related Art:
Conventional general flash memories are classified into the type using hot electron injection for writing and the type using an FN tunnel current for writing.
FIG. 47 is a sectional view of memory cells of a conventional flash memory 500 of the type using hot electron injection. FIG. 48 is an equivalent circuit of a memory cell array of the flash memory 500.
Referring to FIG. 47, the flash memory 500 includes a semiconductor substrate 151, a tunnel insulating film 153 formed on the semiconductor substrate 151, and floating gates 155 formed on the tunnel insulating film 153. An insulating film 156 made of ONO(SiO.sub.2 /SiN/SiO.sub.2) and the like is formed covering the floating gates 155. Control gates 157 are formed on the insulating film 156. As shown in FIG. 48, memory cells (memory cells C.sub.51 to C.sub.53 and C.sub.61 to C.sub.63 are shown in FIG. 48) are arranged in a matrix. The control gates 157 of the memory cells lined in an X direction shown in FIG. 47 are electrically connected to one another, forming a word line WL (word lines WL.sub.1 and WL.sub.2 are shown in FIG. 48).
As shown in FIG. 47, an impurity diffusion layer (a source/drain diffusion layer) 161 is formed between every two memory cells adjacent in the X direction, and shared by the two memory cells as a source diffusion layer 159 for one memory cell and a drain diffusion layer 160 for the other memory cell. Such source/drain diffusion layers are formed in a self-aligning manner by ion implantation using a film as a mask during the fabrication process. Upon completion of the fabrication process, the film will become the floating gates 155 formed in a stripe shape.
As shown in FIG. 48, bit lines BL (bit lines BL.sub.1 to BL.sub.4 are shown in FIG. 48) extend in the Y direction, electrically connecting the diffusion layers 161 lined in the Y direction with one another. Each bit line serves as a source wiring or a drain wiring depending on the selected memory cell. Such a driving method where each bit line is not fixed as the source wiring or the drain wiring, but where the source wiring (ground line) and the drain wiring are appropriately switched is called a virtual ground method.
In the virtual ground method, since the impurity diffusion layer 161 is used both as the source diffusion layer 159 for one memory cell and the drain diffusion layer 160 for a memory cell adjacent in the X direction as described above, no isolation region is required between the source diffusion layer 159 for one memory cell and the drain diffusion layer 160 for the-adjacent memory cell in the X direction. Furthermore, since the bit lines BL are formed by connecting the impurity diffusion layers 161 lined in the Y direction via diffusion wirings, no contact regions are required for the connection of the bit lines BL with the memory cells. This makes it possible to realize high integration of memories.
Japanese Laid-Open Patent Publication No. 2-231772, for example, discloses the configuration shown in FIG. 51, where two memory cells adjacent in the X direction are paired, sharing a source line SL but having individual bit lines BL. This configuration allows for parallel reading and parallel writing of data.
Referring to FIG. 48, the write operation of a flash memory 500 is conducted in the following manner. Assume that the memory cell C.sub.52 is selected as a memory cell in which data is to be written (hereinafter, such a selected memory cell is referred to as a selected cell). First, a high voltage is applied to the word line WL.sub.1 connected with the selected cell C.sub.52. Simultaneously, a predetermined voltage is applied to one of the bit lines connected with the selected cell C.sub.52 (e.g., the bit line BL.sub.3) to define the drain side, while a ground voltage (0 V) is applied to the other bit line (e.g., the bit line BL.sub.2) to define the source side. As a result, hot electrons generated in a channel region of the selected cell C.sub.52 are injected into the floating gate 155, allowing data to be written in the memory cell C.sub.52. At this time, for the other memory cells where no data is written (hereinafter, such memory cells are referred to as non-selected cells), certain voltages are applied to two bit lines connected with any one of the non-selected cells so that the two bit lines have the same potential. For example, for the non-selected cell C.sub.51, voltages are applied to the bit lines BL.sub.3 and BL.sub.4 so that the potentials of these bit lines are the same.
The erase operation of the flash memory 500 is conducted in the following manner. A negative voltage is applied to the word lines WL, and simultaneously, a predetermined positive voltage is applied to all the bit lines BL (or all bit lines in a block when the memory cell array is divided into blocks). This causes an FN tunnel current to flow, drawing out charges accumulated in the floating gates 155 and thus erasing data stored in all the memory cells (or all memory cells in the block) at one time.
The read operation of the flash memory 500 is conducted in the following manner. A predetermined voltage is applied to a word line WL connected with a selected cell for reading. Simultaneously, a predetermined voltage is applied to one of two bit lines connected with the selected cell, while a ground voltage (0 V) is applied to the other bit line. The amount of current flowing between the two bit lines is different depending on the amount of charge (i.e., data) stored in the floating gate 155. The data is thus read by detecting the amount of current. At this time, voltages are applied to two bit lines connected with a non-selected cell where no reading is conducted so that the potential of the two bit lines is the same as in the write operation.
The write operation using the channel hot electron injection as described above has the following drawbacks. The efficiency of electron injection (write efficiency) is generally poor. Since the write current is large (about 1 mA), power consumption at writing is large. A high-voltage power source (or a booster) is required to supply the comparatively large write current, which prevents the flash memory 500 from lowering the driving voltage and using a single power source.
In contrast, a flash memory using an FN tunnel current for writing requires a write current of only about several tens of nanoamps (nAs). Therefore, this type of flash memory can use a single power source. FIG. 49 is a sectional view of memory cells of a conventional flash memory 600 of the type using an FN tunnel current for writing. FIG. 50 is an equivalent circuit of a memory cell array of flash memory 600. Similar components to those of flash memory 500 shown in FIGS. 46 and 47 are denoted by the same reference numerals.
Referring to FIG. 49, the flash memory 600 includes a semiconductor substrate 151, a tunnel insulating film 153 formed of a uniform oxide film on the semiconductor substrate 151, and floating gates 155 formed on the tunnel insulating film 153. A source diffusion layer 159 and a drain diffusion layer 160 are formed on both ends of each of the floating gates 155. An element isolation film 162 is formed between every two adjacent memory cells, isolating the source diffusion layer 159 of one memory cell from the drain diffusion layer 160 of the other memory cell. An insulating film 156 made of ONO (SiO.sub.2 /SiN/SiO.sub.2) is formed covering the floating gates 155. Control gates 157 are formed on the insulating film 156.
Referring to FIG. 50, memory cells (memory cells C.sub.71 to C.sub.73 and C.sub.81 to C.sub.83 are shown in FIG. 50) are arranged in a matrix. The control gates 157 of the memory cells lined in the X direction shown in FIG. 50 are electrically connected with one another, forming a word line WL (word lines WL.sub.1 and WL.sub.2 are shown in FIG. 50). Bit lines BL (bit lines BL.sub.1 to BL.sub.6 are shown in FIG. 50) extend in the Y direction, electrically connecting the corresponding source diffusion layers 159 or the drain diffusion layers 160 with one another. The function of each bit line BL is fixed as the source line or the drain line.
The write operation of the flash memory 600 is conducted in the following manner. A negative voltage or 0 V is applied to the word line WL connected with a selected cell, while a positive voltage is applied to the drain diffusion layer 160 of the connected cell so that electrons are drawn out of the floating gate 155. The erase operation is conducted in the following manner. A positive high voltage is applied to one word line WL, while 0 V is applied to the source diffusion layers 159 and the drain diffusion layers 160 so that electrons are injected into the floating gates of all the memory cells connected with the word line WL.
FIG. 51 shows another example of the flash memory 700 using an FN tunnel current. In the memory cell 600 of FIG. 49, the drain diffusion layer and the source diffusion layer cell of the adjacent memory cells are isolated from each other. In the flash memory 700 of FIG. 51, the drain diffusion layers of respective memory cells are separated from one another and these individual drain diffusion layers lined in the Y direction are connected with one another to form a bit line. Simultaneously, each pair of memory cells adjacent in the X direction share the source diffusion layer to form a source line extending in the Y direction.
However, the conventional flash memory of the type using an FN tunnel current has the following drawbacks. As described above, in the conventional memory using an FN tunnel current for writing, a tunnel current generated by the electric field applied to the tunnel insulating film 153 is used. Accordingly, if in the memory cells shown in FIG. 49, each pair of memory cells adjacent in the X direction share the diffusion layer as shown in FIG. 48, data will be written in a non-selected memory cell which shares the drain diffusion layer with a selected memory cell in data is to be written and is connected with the same word line as the selected memory cell. Accordingly, it is necessary to form the element isolation film 162 as shown in FIG. 49 and isolate at least the drain diffusion layers 160 of the adjacent memory cells in the X direction from each other as shown in FIGS. 50 and 51. Thus, the conventional flash memory of the type using an FN tunnel current for writing cannot employ the virtual ground method. This prevents the flash memory of this type from being made smaller.
As shown in FIG. 49, the tunnel insulating film 153 is comparatively thin. Accordingly, when a comparatively high voltage is applied to the drain diffusion layer 160 at writing, a current 10.sup.6 times the write current may sometimes flow from the end of the drain diffusion layer 160 to the substrate 151 due to the interband tunnel phenomenon.
As the tunnel insulating film 153 becomes thinner, the capacitance between the floating gate and the substrate is larger. This makes it difficult to increase the capacitance coupling ratio of the control gate. Also, as the tunnel insulating film 153 becomes thinner, the disturb margin against a high voltage to be applied to the control gate electrode at writing becomes smaller.